Technical blog
Written companions to our video series: real chip-design flows in G2 with open-source EDA, step by step, with the numbers.
G2 Getting Started: from download to signoff timing
Install G2, build a Nangate45 demo project, take gcd through Yosys, OpenROAD, OpenRCX and OpenSTA, trace data with DDM, compare runs, debug timing with tpath and let the AI assistant run flows. The written companion to the 8-episode video series.
RISC-V RTL-to-Signoff
A real RISC-V core (lowRISC Ibex, instruction cache on, 4 SRAM macros) from RTL to signoff on sky130 with open-source EDA in G2: timing-driven Yosys synthesis, OpenROAD from init to finish, OpenRCX and OpenSTA. The written companion to the 12-episode video series.
RISC-V SoC: Block to Chip
Turning the lowRISC Ibex demo system into a sky130 chip with G2 and open-source EDA (Yosys, OpenROAD, OpenRCX, OpenSTA): RAM macro, PLL, pad ring, hard macro, synthesis, place and route and signoff. The written companion to the 13-episode video series.
RISC-V Flip-Chip: Pads to Bumps
Converting a sky130 RISC-V SoC from wirebond to flip-chip with G2 and open-source EDA: a stand-in RDL layer and bumps, area IO, power bumps and IR drop, hold repair and signoff, compared with the wirebond chip. The written companion to the 8-episode video series.
Earlgrey in G2
OpenTitan Earlgrey, a 1.13-million-cell RISC-V SoC, from RTL to signoff timing with open-source EDA, organized by G2 and built with Claude Code. Six articles and 13 videos: flat vs hierarchical, floorplan from data, two OpenROAD bugs fixed upstream, and what it costs on one laptop.